Amiga Hardware / Motorola 68000
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$A01000 Amiga Models $CPU000 Motorola 68000 $BFE001 CIA 8520 $DFF000 Custom Chips $000000 Memory Organization $DFF096 DMA & Interrupts $DFF080 Copper Coprocessor $DFF100 Playfields & Display $DFF120 Sprites $DFF040 Blitter $DFF0A0 Audio System $JOY00A Mouse & Joystick $DFF030 Serial Port $DFF020 Disk Controller $KBD001 Keyboard $CONN01 Connectors
$CPU000

Processor Overview

The Motorola 68000 is the central processor of the Amiga. Running at 7.09 MHz (PAL) or 7.16 MHz (NTSC), it provides a 32-bit internal architecture with a 16-bit external data bus and a 24-bit address bus, giving access to 16 MB of address space. While the custom chipset handles graphics, sound, and I/O autonomously via DMA, the 68000 runs the operating system and user programs.

The 68000 is packaged in a 64-pin DIP (Dual Inline Package). In the Amiga 500, it sits on the right side of the motherboard — the tallest chip on the board.

Key Specifications

  • Clock: 7.09 MHz (PAL) / 7.16 MHz (NTSC)
  • Data bus: 16-bit external (D0–D15), 32-bit internal
  • Address bus: 23 lines (A1–A23), byte-addressable via UDS/LDS
  • Registers: 8 data (D0–D7), 7 address (A0–A6), USP, SSP, PC, SR
  • Instruction set: CISC, variable-length (2–10 bytes)
  • Modes: User and Supervisor
$CPU000

Pin Configuration

The 68000's 64 pins are organized into functional groups for data transfer, addressing, bus control, and interrupt handling.

Data & Address Bus
D0–D1516-bit bidirectional data bus
A1–A2323-bit address bus (A0 is encoded via UDS/LDS)
Bus Control Signals
AS̄Address Strobe — active low, indicates valid address on bus
R/W̄Read/Write — high=read, low=write
UDS̄Upper Data Strobe — active low, selects upper byte (D8–D15), even address
LDS̄Lower Data Strobe — active low, selects lower byte (D0–D7), odd address
DTACK̄Data Transfer Acknowledge — peripheral signals transfer complete

The 68000 uses an asynchronous bus protocol. Each bus cycle begins when the processor asserts AS̄ with a valid address. The addressed device responds by asserting DTACK̄ when data is ready. If no device responds, the bus cycle waits indefinitely — the Amiga's Gary chip generates DTACK̄ for internal address ranges.

Function Codes
FC0–FC23-bit function code indicating address space type
FC2 FC1 FC0 Address Space
001User Data
010User Program
101Supervisor Data
110Supervisor Program
111Interrupt Acknowledge
$CPU000

Interrupts

The 68000 supports 7 interrupt priority levels. Three input pins (IPL0̄–IPL2̄) encode the pending interrupt level. The processor compares this against the interrupt mask in the status register and services the interrupt if the pending level is higher (level 7 is non-maskable).

Interrupt Pins
IPL0̄–IPL2̄Interrupt Priority Level — active low, encoded (111=no interrupt, 000=level 7 NMI)

In the Amiga, the custom chips and CIAs generate interrupts that Paula prioritizes and routes to the 68000:

Level Vector Priority Sources
1$064LowestSoftware interrupt, disk sync, serial TBE
2$068CIA-A (I/O ports, timers, TOD)
3$06CCopper, VBL, Blitter finished
4$070Audio channels 0–3
5$074Serial receive, disk DMA
6$078CIA-B (parallel port, timers)
7$07CNMINon-maskable (active only with expansion hardware)
$CPU000

Bus Arbitration

The 68000 shares the bus with the custom chipset's DMA controller (Agnus). Three signals manage bus ownership:

Bus Arbitration Signals
BR̄Bus Request — DMA controller requests bus ownership
BḠBus Grant — 68000 acknowledges, will release bus after current cycle
BGACK̄Bus Grant Acknowledge — DMA controller confirms bus takeover

In practice, Agnus "steals" cycles from the 68000 transparently. The Amiga's bus timing divides each 280 ns bus cycle into odd and even slots. DMA channels (bitplane, sprite, audio, disk, Copper, Blitter) use specific slots, and the 68000 gets whatever remains.

When BLTPRI is set in DMACON, the Blitter takes absolute priority over the 68000, which can freeze the processor for the duration of large blits.

$CPU000

System Control

System Control Pins
HALT̄Halts the processor — bidirectional. Processor drives low on double bus fault.
RESET̄System reset — bidirectional. External reset initializes processor; RESET instruction in supervisor mode resets peripherals without affecting CPU state.
BER̄RBus Error — signals invalid bus cycle, triggers exception processing
VPĀValid Peripheral Address — signals 6800-compatible synchronous bus cycle (used for CIA access)
EEnable — clock output at CLK/10 for 6800-family peripherals (CIAs)
VMĀValid Memory Address — processor acknowledges synchronous cycle

The E clock runs at approximately 709 kHz (CLK÷10) and provides the timing reference for the two CIA 8520 chips. Access to the CIAs uses the 6800-compatible synchronous bus protocol (VPĀ/VMĀ/E) rather than the standard asynchronous protocol (DTACK̄), which means CIA accesses are inherently slower than custom chip register accesses.