All data flowing between the custom chips and Chip RAM passes through DMA (Direct Memory Access) channels controlled by Agnus. The 68000 CPU is just one of many bus masters competing for access to memory. Each custom chip subsystem — bitplanes, sprites, disk, audio, Copper, and Blitter — has its own DMA channel that can read or write Chip RAM independently of the processor.

DMA transfers work through three types of registers for each I/O unit:

• Control registers — programmed by the CPU to configure parameters (resolution, volume, disk track, etc.)
• Data registers — hold the actual data being transferred between the unit and Chip RAM
• Address registers (pointers) — tell the DMA controller where in Chip RAM to read from or write to

The central DMA control register, DMACON, enables or disables each channel individually. A master enable bit must also be set for any channel to operate.

The Six DMA Channels

Bitplane DMA — reads display data from Chip RAM into the bitplane data registers, feeding the video sequencers in Denise for screen output.

Sprite DMA — transfers sprite image data from Chip RAM into sprite data registers.

Disk DMA — bidirectional transfer of floppy disk data between the disk controller and Chip RAM.

Audio DMA — reads digitized sound sample data from Chip RAM into the audio channel data registers.

Copper DMA — fetches Copper coprocessor instructions from Chip RAM.

Blitter DMA — transfers data to and from the Blitter for area fill, line draw, and block copy operations.

The Amiga's bus timing is synchronized to the video raster. One horizontal raster line lasts approximately 63.5 microseconds and comprises 227.5 bus cycles. Each bus cycle is about 280 nanoseconds — during which one memory access can occur.

Odd and Even Cycles

The key insight to Amiga bus architecture is the division of cycles into odd and even:

• Odd cycles are reserved exclusively for DMA. The 68000 cannot use them.
• Even cycles are shared between the CPU, Copper, and Blitter. DMA always has priority.

The 68000 runs at a clock frequency that only allows one memory access every 560 ns — exactly two bus cycles. It can therefore only claim every other (even) cycle. This means the odd-cycle DMA channels (sprites, audio, disk, refresh) operate without slowing down the processor at all.

DMA Priority and Cycle Assignment

Within each raster line, DMA slots are assigned in a fixed order:

In low resolution with 4 or fewer bitplanes, all bitplane data fits in odd cycles, leaving even cycles free for the CPU. With 5 or 6 bitplanes in lores, two even cycles per 8-cycle group are consumed by bitplane DMA, reducing CPU bandwidth. In high resolution, 2 bitplanes fit in odd cycles, but 3 or 4 hires bitplanes steal even cycles — the CPU can lose over half its bus time.

Programs running from Fast RAM or Kickstart ROM are unaffected by DMA contention, since those buses are independent of the Chip RAM bus.

The Amiga's video output follows the PAL standard (or NTSC in North American models). Understanding the raster is essential because all DMA timing is derived from it.

PAL Timing

A PAL frame consists of 625 lines at 50 fields per second. To avoid flicker while keeping line frequency manageable (15,625 Hz), the image is split into two interlaced fields:

• Long Frame (odd lines: 1, 3, 5, ... 625) — 313 lines
• Short Frame (even lines: 2, 4, 6, ... 624) — 312 lines

In the Amiga's default non-interlaced mode, both fields display the same 313 lines at 50 Hz, producing a stable image with visible line spacing. Interlace mode can be enabled to double vertical resolution to 625 lines, at the cost of visible flicker on high-contrast horizontal edges.

Beam Position Registers

Agnus maintains an internal counter tracking the electron beam's position. The CPU can read this counter to determine exactly where in the frame it is.

Horizontal positions range from $00 to $E3 (0–227), with $0F–$35 corresponding to the horizontal blanking interval. Vertical lines 0–25 are the vertical blanking interval, with the visible area starting at line 26 and extending to line 312.

The LOF bit indicates which field type is currently being displayed — set for Long Frame (odd lines), clear for Short Frame (even lines). In non-interlaced mode, LOF is always 1.

The DMACON register is the central switch for all DMA channels. It uses a SET/CLR mechanism: you cannot write it directly, only set or clear individual bits.

SET/CLR Mechanism

DMACON cannot be written like an ordinary register. Instead, bit 15 determines the operation:

• Bit 15 = 1: All bits set to 1 in the written value will be set in DMACON. Other bits are unchanged.
• Bit 15 = 0: All bits set to 1 in the written value will be cleared in DMACON. Other bits are unchanged.

A DMA channel is active only when both its individual enable bit and the master DMAEN bit (bit 9) are set.

    ; Enable bitplane and Copper DMA:
    MOVE.W #$8380,$DFF096    ; SET/CLR=1, DMAEN=1, BPLEN=1, COPEN=1

    ; Disable Blitter DMA only:
    MOVE.W #$0040,$DFF096    ; SET/CLR=0, BLTEN=1 → clears BLTEN

Blitter Priority (BLTPRI)

When BLTPRI is set, the Blitter takes absolute priority over the 68000 — the CPU gets no even-cycle bus access during Blitter operations. When clear, the CPU is granted one cycle out of every four even bus cycles, preventing it from being locked out entirely. This is critical when the CPU must service time-sensitive interrupts or access OS data structures in Chip RAM.

The Amiga's interrupt system is managed by PAULA, which collects interrupt requests from all sources and generates the appropriate 68000 interrupt level signals. There are 14 interrupt sources organized into 6 priority levels (level 7 / NMI is not used).

Two registers control the system, both using the same SET/CLR mechanism as DMACON:

Both INTREQ and INTENA share the same bit layout:

How Interrupts Fire

For an interrupt to reach the 68000, three conditions must be met:

1. The corresponding bit in INTREQ is set (the hardware source is requesting service)
2. The corresponding bit in INTENA is set (the source is enabled)
3. The INTEN bit (bit 14) in INTENA is set (master enable is on)

When all three conditions are true, PAULA asserts the appropriate interrupt level on the 68000's IPL pins.

Acknowledging Interrupts

After servicing an interrupt, the handler must clear the corresponding bit in INTREQ by writing to it. The hardware does not auto-clear request bits. For CIA interrupts, note that reading the CIA's ICR register clears the CIA-side flags, but the corresponding INTREQ bit (3 for CIA-A, 13 for CIA-B) must still be explicitly cleared.

The 68000 uses autovectored interrupts on the Amiga. Each priority level maps to a fixed vector address:

Higher level numbers indicate higher priority. A level 6 interrupt can preempt a level 3 handler, but not vice versa. Since multiple sources share a level, the interrupt handler must read INTREQR to determine which source triggered the interrupt.

CIA Interrupt Routing

The two CIAs route their interrupts through PAULA differently:

• CIA-A triggers the PORTS interrupt (bit 3, level 2). The specific CIA-A source is identified by reading CIA-A's ICR register.
• CIA-B triggers the EXTER interrupt (bit 13, level 6). The specific CIA-B source is identified by reading CIA-B's ICR register.

Both PORTS and EXTER can also be triggered by expansion cards on the Zorro bus.

Software Interrupts and Copper Interrupts

The SOFT bit (bit 2) allows software to generate a level 1 interrupt by writing to INTREQ. The Copper can also generate interrupts — since it can only perform MOVE operations, it triggers the COPER interrupt (bit 4, level 3) by writing the appropriate value to INTREQ:

    ; Copper instruction to trigger an interrupt:
    MOVE #$8010,INTREQ    ; SET bit 4 (COPER) in INTREQ

The VERTB interrupt (bit 5, level 3) fires at the start of every vertical blank period (line 0), 50 times per second in PAL. This is the primary timing reference for frame-synchronized operations — updating animation, reading input, and reinitializing bitplane pointers via the Copper.